ST7FLCD1 datasheet(63/95 Pages) STMICROELECTRONICS

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ST7FLCD1

Display Data Channel Interfaces (DDC)

EDID DMA Pointer Configuration).

11.4.2 Mode Description

DDC2B Mode: The DDC2B Interface enters DDC2B mode from the initial state if the software sets

the HWPE bit. Once in DDC2B mode, the Interface always acts as a slave following the protocol

described in Figure 34.

The DDC2B Interface continuously monitors the SDA and SCL lines for a START condition and will

not respond (no acknowledge) until one is found.

A STOP condition at the end of a Read command (after a NACK) forces the stand-by state. A STOP

condition at the end of a Write command triggers the internal DMA write cycle.

The Interface samples the SDA line on the rising edge of the SCL signal and outputs data on the

falling edge of the SCL signal. In any case, the SDA line can only change when the SCL line is low.

EDID Data structure mapping: An internal address pointer defines the memory location being

addressed.

Figure 34: DDC2B Protocol Example

Figure 35: DDC1/2B Operation Flowchart

SDA

SCL

Start

Ack

A0h

Device Slave

00h

Data Address

Ack

Start A1h

Data1

Ack

DataN

Nack

Stop

Address

Device Slave

Address

128 / 256 bytes EDID

Legend:

Italics = data / control signal from display

Ack

Bold = data / control signal from host

Wait for HWPE = 1

HWPE bit = 0

Received valid

Device Address?

Respond to Command

Send Acknowledge

DMA Low Pointer Address = 0

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