ST7FLCD1 datasheet(66/95 Pages) STMICROELECTRONICS

66 / 95 page

Display Data Channel Interfaces (DDC)

ST7FLCD1

66/95

Read and Write Operations

After each byte transfer, the internal address counter automatically increments. If the counter is

pointing to the top of the structure, it rolls over to the bottom since the increment is performed only

on the 7 or 8 LSBs of the pointer depending on the selected data structure size. It rolls over from

7Fh to 00h or from FFh to 80h depending on the MSB of the last data address received.

Then after that last byte has been effectively written or read in RAM at LSB address 7Fh or FFh, the

EDF flag is set and an interrupt is generated if EDE is set.

The transfer is terminated by the master generating a STOP condition.

11.5

DDC/CI Factory Alignment Interface

Refer to the CR, SR1 and SR2 registers in Section 11.7: Register Description for the bit definitions.

The DDC/CI interface works as an I/O interface between the microcontroller and the DDC2Bi,

HDCP, E-DDC or Factory alignment protocols. It receives and transmits data in Slave I²C mode

using an interrupt or polled handshaking.

The interface is connected to the I²C bus through a data pin (SDAD) and a clock pin (SCLD)

configured as an open-drain output.

The DDC/CI interface has five internal register locations. Two of them are used to initialize the

interface:

1. 2 Own Address Registers OAR1 and OAR2

2. Control register CR

The following four registers are used during data transmission/reception:

1. Data Register DR

2. Control Register CR

3. Status Register 1 SR1

4. Status Register 2 SR2

The interface decodes an I²C or DDC2Bi address stored by software in either OAR register and/or

the DDC/CI address (6Eh/6Fh) as its default hardware address.

After a reset, the interface is disabled.

11.5.1 I²C Modes

The interface operates in Slave Transmitter/Receiver modes.

The master generates both Start and Stop conditions. The I²C clock (SCL) is always received by the

interface from a master, but the interface is able to stretch the clock line.

The interface can recognize its two programmable addresses (7-bit) and its default hardware

address (DDC/CI address: 6Eh/6Fh). The DDC/CI address detection may be enabled or disabled by

software. It never recognizes the Start byte (01h) whatever its own address is.

Slave mode

As soon as a start condition is detected, the address is received from the SDA line and sent to the

shift register where it is compared to the programmable addresses or to the DDC/CI address (if

selected by software).

Address not matched: the interface ignores it and waits for another Start condition.

Address matched: the following events occur in sequence:

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