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ST7FLCD1 数据表(PDF) 42 Page - STMicroelectronics |
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ST7FLCD1 数据表(HTML) 42 Page - STMicroelectronics |
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42 / 95 page  I/O Ports ST7FLCD1 42/95 7.7 Register Description DATA REGISTERS (PXDR) DATA DIRECTION REGISTERS (PXDDR) (‘x’ corresponds to the I/O pin of the associated port. In Input mode, the value is 00h by default).I Figure 22: Port D Table 15: I/O Port Register Map Address Reset Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0002h 00h R/W PADR PADR[7:0] 0003h 00h R/W PADDR PADDR[7:0] 0004h 00h R/W PBDR PBDR[7:0] 0005h 00h R/W PBDDR PBDDR[7:0] 0006h 00h R/W PCDR PCDR[7:0] 0007h 00h R/W PCDDR PCDDR[7:0] 0008h 00h R/W PDDR PDDR[7:0] 0009h 00h R/W PDDDR PDDDR[7:0] DR SEL DDR SEL 1 0 TTL Schmitt Trigger DR DDR Latch Latch VSS Alternate Input Alternate Output Enable Alternate 1 0 output Alternate Output Enable |
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