ST7FLCD1 datasheet(70/95 Pages) STMICROELECTRONICS

70 / 95 page

Display Data Channel Interfaces (DDC)

ST7FLCD1

70/95

Bit 5 = PE DDC/CI Peripheral enable.

This bit is set and cleared by software.

Peripheral disabled

Peripheral enabled

Note:

When PE = 0, all the bits of the CR, SR1 and SR2 registers are reset.

All outputs are released when PE = 0

When PE = 1, the corresponding I/O pins are selected by hardware as alternate functions.

To enable the I²C interface, write the CR register TWICE with PE = 1 as the first write only activates

the interface (only PE is set).

Bit 4 = DDCCIEN DDC/CI address detection enabled.

This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled

(PE = 0). The 6Eh/6Fh DDC/CI address is acknowledged.

DDC/CI address detection disabled

DDC/CI address detection enabled

Bit 3 = Reserved. Forced to 0 by hardware.

Bit 2 = ACK Acknowledge enable.

This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled

(PE = 0).

No acknowledge returned

Acknowledge returned after an address byte or a data byte is received

Bit 1 = STOP Release I²C bus.

This bit is set and cleared by software or when the interface is disabled (PE = 0).

Slave Mode:

Nothing

Release the SCL and SDA lines after the current byte transfer (BTF = 1). The STOP bit has to

be cleared by software.

Bit 0 = ITE Interrupt enable.

This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE

= 0).

Interrupt disabled

Interrupt enabled

Refer to Figure 39 for the relationship between the events and the interrupt.

SCL is held low when the BTF or ADSL is detected.

DDC STATUS REGISTER 1 (DDCSR1)

Read Only

Reset Value: 0000 0000 (00h)

321

EVF

TRA

BUSY

BTF

ADSL

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