ST7FLCD1 datasheet(84/95 Pages) STMICROELECTRONICS

84 / 95 page

Infrared Preprocessor (IFR)

ST7FLCD1

84/95

The IFR input signal is preprocessed by a spike filter. This filter removes all pulses with a positive

level that lasts less than 2 µs or 160 µs, depending on the FLSEL bit. The negative level can be of

any duration and is never filtered out.

Note:

If the interrupt is enabled but no signal is detected, an interrupt occurs every 20.4 ms.

15.3

INFRA RED DATA REGISTER (IFRDR)

Read/Write

Reset Value: (00h)

Bits [7:0] = IR[7:0] Infra red pulse width

The 8-bit counter value is transferred in this register when an expected edge occurs on the IFR pin

or when the counter overflows. A write to this register resets the internal overflow flag.

INFRA RED CONTROL REGISTER (IFRCR)

Read/Write

Reset Value: (00h)

Bits [7:5] = Reserved. Forced by hardware to 0.

Bit 4 = ITE Interrupt enable

Interrupt disabled

Interrupt enabled. It is generated when an edge (falling and/or rising depending on bits POSED

and NEGED) occurs or after a counter overflow.

Bit 3 = FLSEL Spike filter pulse width selection

Filter positive pulses narrower than 2 µs

Filter positive pulses narrower than 160 µs

Bits [2:1] = POSED, NEGED Edge selection for the duration measurement

Bit 0 = Reserved. Forced by hardware to 0.

321

IR7

IR6

IR5

IR4

IR3

IR2

IR1

IR0

321

ITE

FLSEL

POSED

NEGED

Table 30: Duration Measurement

POSED

NEGED

Count latch at...

When count reaches 255

Negative transition of IFR or when count reaches 255

Positive transition of IFR or when count reaches 255

Positive or negative transition of IFR or when count reached 255

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