ST7FLCD1 datasheet(58/95 Pages) STMICROELECTRONICS

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I²C Single-Master Bus Interface

ST7FLCD1

58/95

generation if ITE = 1. It is cleared by software by reading the SR register followed by a read or write

of DR register. It is also cleared by hardware when the interface is disabled (PE = 0).

Following a byte transmission, this bit is set after reception of the acknowledge clock pulse. In case

an address byte is sent, this bit is set only after the EV2 event (See Section 10.5: Transfer

Sequencing). BTF is cleared by reading SR register followed by writing the next byte in DR register.

Following a byte reception, this bit is set after transmission of the acknowledge clock pulse if

ACK = 1. BTF is cleared by reading SR register followed by reading the byte from DR register.

The SCL line is held low when BTF = 1.

Byte transfer not done

Byte transfer succeeded

Bit 2 = Reserved. Forced to 0 by hardware.

Bit 1 = M/IDL Master/Idle.

This bit is set by hardware when the interface is in Master mode (writing START = 1). It is cleared by

hardware after a Stop condition on the bus. It is also cleared by hardware when the interface is

disabled (PE = 0).

Idle mode

Master mode

Bit 0 = SB Start bit.

This bit is set by hardware when a Start condition is generated (following a write START = 1). An

interrupt is generated if ITE = 1. It is cleared by software by reading the SR register followed by

writing the address byte in DR register. It is also cleared by hardware when the interface is disabled

(PE = 0).

No Start condition

Start condition generated

I²C CLOCK CONTROL REGISTER (I2CCCR)

Read / Write

Reset Value: 0000 0000 (00h)

Bit 7 = FM/SM Fast/Standard I²C mode.

This bit is set and cleared by software. It is not cleared when the interface is disabled (PE = 0).

Fast I²C mode

Standard I²C mode

Bit 6 = FILTOFF Filter Off.

This bit is set and cleared by software, it is not taken into account in the EMU version and is

considered as always set to 1 (inactive filter).

When set, it disables the filter of the I²C pads in order to achieve speeds of over 400 kHz on a short-

length I²C bus (at the user’s responsibility). Such high frequencies are computed with the Fast mode

formula given below.

321

FM/SM

FILTOFF

CC5

CC4

CC3

CC2

CC1

CC0

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