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ST7FLCD1 数据表(PDF) 27 Page - STMicroelectronics |
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ST7FLCD1 数据表(HTML) 27 Page - STMicroelectronics |
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27 / 95 page  27/95 ST7FLCD1 Interrupts ** Many flags can cause an interrupt, see peripheral interrupt status register description. Table 7: Interrupt Mapping Source Block Description Register Flag Maskable Vector Address Priority Order RESET Reset N/A N/A No FFFEh to FFFFh TRAP Software N/A N/A No FFFCh to FFFDh Not used FFFAh to FFFBh DDC/CI A DDC Interrupt DDCSR1A DDCSR2A ** Yes FFF8h to FFF9h DDC2B A End of communication Interrupt DDCDCRA ENDCF Yes FFF6h to FFF7h End of download Interrupt EDF Yes FFF6h to FFF7h DDC/CI B DDC Interrupt DDCSR1B DDCSR2B ** Yes FFF4h to FFF5h DDC2B B End of communication Interrupt DDCDCRB ENDCF Yes FFF2h to FFF3h End of download Interrupt EDF Yes FFF2h to FFF3h Not used FFF0h to FFF1h IFR IFR Interrupt IFRCR Yes FFEEh to FFEFh Port A bit 6 External Interrupt ITA ITRFRE ITALAT FFECh to FFEDh Port A bit 7 External Interrupt ITB ITRFRE ITBLAT Yes FFEAh to FFEBh I²C I²C Peripheral Interrupts I2CSR1 I2CSR2 ** Yes FFE8h to FFE9h Not used FFE6h to FFE7h TIMB Timer B overflow TIMCSRB TOF Yes FFE4h to FFE5h TIMA Timer A overflow TIMCSRA TOF Yes FFE2h to FFE3h Not used FFE0h to FFE1h Priority Highest Priority Lowest |
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