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ST7FLCD1 数据表(PDF) 79 Page - STMicroelectronics |
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ST7FLCD1 数据表(HTML) 79 Page - STMicroelectronics |
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79 / 95 page  79/95 ST7FLCD1 8-bit Timer (TIMA) Bit 0 = BUZE Buzzer enable This bit is set and cleared by software. 0 Buzzer disabled 1 Buzzer enabled. It has priority over any other alternate function mapped onto the same pin (PWM). TIMER A COUNTER PRELOAD REGISTER (TIMCPRA) Read/Write Reset Value: (00h) Bits [7:0] = PR[7:0] Counter Preload Data These bits are set and cleared by software. They are used to hold the reload value which is immediately loaded in the counter. Note: The N number loaded in TIMCPRA register corresponds to a time of (N + 1) x Period timer. The "00" value is prohobited. 76 54 321 0 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0 |
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