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ST7FLCD1 数据表(PDF) 69 Page - STMicroelectronics

部件名 ST7FLCD1
功能描述  8-bit MCU for LCD Monitors with 60 KBytes Flash, 2 KBytes RAM, 2 DDC Ports and Infrared Controller
PDF  95 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7FLCD1 数据表(HTML) 69 Page - STMicroelectronics

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ST7FLCD1
Display Data Channel Interfaces (DDC)
11.7
Register Description
DDC CONTROL REGISTER (DDCCR)
Read / Write
Reset Value: 0000 0000 (00h)
Bits [7:6] = Reserved. Forced to 0 by hardware.
Table 22: DDCA Register Map
Address Reset
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0020h
00h
R/W
DDCCRA
0
0
PE
DDCCIEN
0
ACK
STOP
ITE
0021h
00h
R
DDCSR1A
EVF
0
TRA
BUSY
BTF
ADSL
0
0
0022h
00h
R
DDCSR2A
0
0
0
AF
STOPF
0
BERR
DDCIF
0023h
00h
R/W DDCOAR1A
ADD[7:1]
0
0024h
00h
R/W DDCOAR2A
ADD[7:1]
0
0025h
00h
R/W
DDCDRA
DR[7:0]
0026h
00h
R/W
Reserved
0027h
00h
R/W DDCDCRA
0
0
ENDCF
ENDCE
EDF
EDE
WP
DDC2BPE
Table 23: DDCB Register Map
Address Reset
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0028h
00h
R/W
DDCCRB
0
0
PE
DDCCIEN
0
ACK
STOP
ITE
0029h
00h
R
DDCSR1B
EVF
0
TRA
BUSY
BTF
ADSL
0
0
002Ah
00h
R
DDCSR2B
0
0
0
AF
STOPF
0
BERR
DDCIF
002Bh
00h
R/W DDCOAR1B
ADD[7:1]
0
002Ch
00h
R/W DDCOAR2B
ADD[7:1]
0
002Dh
00h
R/W
DDCDRB
DR[7:0]
002Eh
00h
R/W
Reserved
002Fh
00h
R/W
DDCDCRB
0
0
ENDCF
ENDCE
EDF
EDE
WP
DDC2BPE
Table 24: EDID DMA Pointer Configuration
Cell
Basic EDID
Extended EDID
DDCA
600h to 67Fh
680h to 6FFh
DDCB
700h to 77Fh
780h to 7FFh
76
54
321
0
0
0
PE
DDCCIEN
0
ACK
STOP
ITE



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