ST7FLCD1 datasheet(17/95 Pages) STMICROELECTRONICS

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ST7FLCD1

Central Processing Unit (CPU)

Bit 3 = I Interrupt mask.

This bit is set by hardware by an interrupt or by software that disables all interrupts except the TRAP

software interrupt. This bit is cleared by software.

Interrupts are enabled.

Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM

instructions.

Interrupts requested when the I bit is set are latched and processed when the I bit is cleared. By

default an interrupt routine is not interruptible as the I bit is set by hardware when you enter it and

reset by the IRET instruction at the end of interrupt routine. In case the I bit is cleared by software

during the interrupt routine, pending interrupts are serviced regardless of the priority level of the

current interrupt routine.

Bit 2 = N Negative.

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic,

logical or data manipulation. It is a copy of the 7th bit of the result.

The last operation result is positive or null.

The last operation result is negative (i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical

or data manipulation is zero.

The result of the last operation is different from zero.

The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and software. Informs if an overflow or underflow occurred

during the last arithmetic operation.

No overflow or underflow has occurred.

An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It

is also affected by the “bit test and branch”, shift and rotate instructions.

STACK POINTER (SP)

Read/Write

Reset Value: 01 FFh

000

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

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