ST7FLCD1 datasheet(81/95 Pages) STMICROELECTRONICS

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ST7FLCD1

8-bit Timer with External Trigger (TIMB)

The four possible operating modes are described in Table 28.

Note:1. The downcounter value cannot be read.

2. Change the EXT value to exit the External One-shot mode.

TIMER B CONTROL STATUS REGISTER (TIMCSRB)

Read/Write

Reset value: (00h)

Bits [7:6] = TB[1:0] Time Base period selection

These bits are set and cleared by software.

00 Time base period = tTIMER (16µs @ 8MHz)

01 Time base period = tTIMER x 8 (128 µs @ 8 MHz)

10 Time base period = tTIMER x 16 (256 µs @ 8 MHz)

11 Reserved

Bit 5 = OVF Timer Overflow Flag

This bit is set by hardware. An interrupt is generated if OVFE = 1. It must be cleared by reading the

TIMCSRB register.

No timer overflow

The free running downcounter rolled over from 00h

Table 28: Timer Operating Mode

TAR

EXT

Timer mode

One-shot after the TIMCPRB register write (no auto reload)

One-shot after the external signal detection (no auto reload).

Only the very first external pulse triggers the countdown (Note 2)

Downcounter auto-reload when 00h reached

Downcounter reloaded with TIMCPRB register value, count-down restarts

One-shot for each external signal detection.

Downcounter preloaded with TIMCPRB when 00h reached.

Countdown restarts after the next external signal detection.

Table 29: Timer Controller Register Map

Address

Reset

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0038h

00h

R/W

TIMCSRB

TB1

TB0

OVF

OVFE

TAR

EXT

EDG

EEF

0039h

01h

R/W

TIMCPRB

PR7

PR6

PR5

PR4

PR3

PR2

PR1

PR0

TB1

TB0

OVF

OVFE

TAR

EXT

EDG

EEF

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