ST7FLCD1 datasheet(47/95 Pages) STMICROELECTRONICS

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ST7FLCD1

PWM Generator

DUTY CYCLE REGISTERS (PWMDCRx)

Read/Write

Reset Value 0000 0000 (00h)

Bits [7:0] = DC[7:0] Duty Cycle Data

These bits are set and cleared by software.

A DCRx register is associated with the DCRix register of each PWM channel to determine the

second edge location of the PWM signal (the first edge location is common to all 4 channels and

given by the ARR register). These DCR registers allow the duty cycle to be set independently for

each PWM channel.

CONTROL REGISTER A (PWMCRA)

Read/Write

Reset Value: 0000 0000 (00h)

Bits [7:4] = OE [3:0] PWM Output Enable.

These bits are set and cleared by software. They enable or disable the PWM output channels

independently acting on the corresponding I/O pin.

the PWM pin is a general I/O.

the PWM pin is driven by the PWM peripheral.

Bits [3:0] = OP[3:0] PWM Output Polarity.

These bits are set and cleared by software. They independently select the polarity of the 4 PWM

output signals.

positive polarity.

negative polarity.

Note:

When an OPx bit is modified, the PWMx output signal is immediately updated.

AUTO-RELOAD REGISTER A (PWMARRA)

Read/Write

Reset Value: 1111 1111(FFh)

Bits [7:0] = AR[7:0] Counter Auto-Reload Data.

These bits are set and cleared by software. They are used to hold the auto-reload value which is

automatically loaded in the counter when an overflow occurs. Writing in this register reload the

PWM counter to ARR A value. At the same time, the PWM output levels are changed according to

the corresponding OPx bit in the PWMCR register.

321

DC7

DC6

DC5

DC4

DC3

DC2

DC1

DC0

321

OE3

OE2

OE1

OE0

OP3

OP2

OP1

OP0

321

AR73

AR6

AR5

AR4

AR3

AR2

AR1

AR0

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