ST7FLCD1 datasheet(32/95 Pages) STMICROELECTRONICS

32 / 95 page

Clocks & Low Power Modes

ST7FLCD1

32/95

Clocks & Low Power Modes

6.1

Clock System

6.1.1

General Description

The device requires a certain number of clock signals in order to operate. All clock signals are

derived from the root clock signal CkXT provided at the output of the "OSC" circuit (refer to

Figure 13). If a quartz crystal is applied on pins OSCIN and OSCOUT, the OSC operates in a

crystal-controlled oscillator mode. An external clock signal can also be applied on OSCIN pin,

putting the OSC in external clock mode operation.

The block diagram in Figure 13 shows the basic configuration of the clock system.

6.1.2

Crystal Oscillator Mode

In this mode, the root clock is generated by the on-chip oscillator controlled by an external parallel

fundamental-mode quartz crystal. General design precautions must be followed to ensure

maximum stability. Foot capacitors CL1 and CL2 must be adapted to match the crystal oscillator. A

100-k

W resistor is internally connected between pins OSCIN and OSCOUT.

6.1.3

External Clock Mode

In this mode, an external clock is provided on pin OSCIN, while pin OSCOUT is left open. The signal

is internally buffered before feeding the subsequent stages. There is the same emphasis on stability

of the external clock as in Crystal Oscillator mode.

6.1.4

Clock Signals

The root clock is divided by a factor of 3 to obtain the CPU clock (fCPU).

Figure 13: Main Clock Generation

OSC

CkXT

OSC

CkXT

External

Clock

Crystal Oscillator Mode

External Clock Mode

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