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ST7FLCD1 数据表(PDF) 18 Page - STMicroelectronics |
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ST7FLCD1 数据表(HTML) 18 Page - STMicroelectronics |
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18 / 95 page ![]() Central Processing Unit (CPU) ST7FLCD1 18/95 The Stack Pointer is a 16-bit register always pointing to the next free location in the stack. The pointer value increments when data is taken from the stack, it decrements once data is transferred into the stack (see Figure 6). Since the stack is 256 bytes deep, the most significant byte is forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack highest address. The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around the stack upper limit, without indicating a stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. You can directly manipulate the stack using PUSH and POP instructions. In case of interrupt, the PCL is stored at the first location pointed to by the SP. Other registers are then stored in the next locations as shown in Figure 6. When interrupt is received, the SP value decrements and the context is pushed to the stack. On return from interrupt, the SP value increments and the context is popped from the stack. A subroutine call and interrupt occupy two and five locations in the stack area respectively. Figure 6: Stack Manipulation Example Table 4: Instruction Set (Sheet 1 of 2) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Load and Transfer LD CLR Stack operation PUSH POP RSP Increment/Decrement INC DEC Compare and Tests CP TNZ BCP Logical operations AND OR XOR CPL NEG SP SP SP SP SP Subroutine Call Interrupt Event PUSH Y POP Y IRET RET or RSP h h Stack Higher Address = 01FFh Stack Lower Address = 0100h PCL PCH CC A X PCH PCL PCH PCL CC A X PCH PCL PCH PCL Y CC A X PCH PCL PCH PCL PCL PCH |
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