ST7FLCD1 datasheet(56/95 Pages) STMICROELECTRONICS

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I²C Single-Master Bus Interface

ST7FLCD1

56/95

10.6

I²C CONTROL REGISTER (I2CCR)

Read / Write

Reset Value: 0000 0000 (00h)

Bits [7:6] = Reserved. Forced to 0 by hardware.

Bit 5 = PE Peripheral enable.

This bit is set and cleared by software.

Peripheral disabled

Master capability

Note:

When PE = 0, all the bits of the CR register and the SR register except the Stop bit are reset. All

outputs are released when PE = 0.

When PE = 1, the corresponding I/O pins are selected by hardware as alternate functions.

To enable the I²C interface, write the CR register TWICE with PE = 1 as the first write only activates

the interface (only PE is set).

Bit 4 = Reserved. Forced to 0 by hardware

Bit 3 = START Generation of a Start condition. This bit is set and cleared by software. It is also

cleared by hardware when the interface is disabled (PE = 0) or when the Start condition is sent (with

interrupt generation if ITE = 1).

In Master mode:

No start generation

Repeated start generation

In Idle mode:

No start generation

Start generation when the bus is free

Bit 2 = ACK Acknowledge enable.

This bit is set and cleared by software. Cleared by hardware when the interface is disabled (PE = 0).

No acknowledge returned

Acknowledge returned after an address byte or a data byte is received

Table 21: I²C Register Map

Addr.

(Hex.)

Reset

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

001Ch

00h

R/W

I2CCR

START

ACK

STOP

ITE

001Dh

00h

Read only

I2CSR

EVF

TRA

BTF

M/IDL

001Eh

00h

R/W

I2CCCR

FM/SM

FILTOFF

CC[5:0]

001Fh

00h

R/W

I2CDR

DR7[:0]

321

START

ACK

STOP

ITE

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