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ST7FLCD1 数据表(PDF) 60 Page - STMicroelectronics

部件名 ST7FLCD1
功能描述  8-bit MCU for LCD Monitors with 60 KBytes Flash, 2 KBytes RAM, 2 DDC Ports and Infrared Controller
PDF  95 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7FLCD1 数据表(HTML) 60 Page - STMicroelectronics

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Display Data Channel Interfaces (DDC)
ST7FLCD1
60/95
11
Display Data Channel Interfaces (DDC)
11.1
Introduction
The DDC (Display Data Channel) bus interfaces are mainly used by the monitor to identify itself to
the video controller, by the monitor manufacturer to perform factory alignment, and by the user to
adjust the monitor’s parameters. Both DDC interfaces consist of:
A fully hardware-implemented interface, supporting DDC2B (VESA specification 3.0
compliant). It accesses the ST7 on-chip memory directly through a built-in DMA engine.
A second interface, supporting the slave I²C functions for handling DDC/CI mode (DDC2Bi),
factory alignment, HDCP, Enhanced DDC (EDDC) or other addresses by software.
Each DDC interface has its own dedicated DMA area in RAM. In the event of concurrent DMA
accesses, the DDC A cell has priority over the DDC B cell.
11.2
DDC Interface Features
11.2.1 Hardware DDC2B Interface Features
Full hardware support for DDC2B communications (VESA specification version 3)
Hardware detection of DDC2B addresses A0h/A1h
Separate mapping of EDID version 1: Base (128 bytes) and Extended (128 bytes)
Support for error recovery mechanism
Detection of misplaced Start and Stop conditions
Random and Sequential I²C byte read modes
DMA transfer from any memory location and to RAM
Automatic memory address increment
End of data downloading flag, end of communication flag and interrupt capability
11.2.2 DDC/CI Factory Interface Features
General I²C Features
Parallel bus /I²C protocol converter
Interrupt generation
Standard I²C mode
7-bit Addressing
I²C Slave Features
I²C bus busy flag
Start bit detection flag
Detection of misplaced Start or Stop condition
Transfer problem detection
Address Matched detection
2 Programmable Address detection and/or Hardware detection of DDC/CI addresses (6Eh/
6Fh)
End of byte transmission flag
Transmitter/Receiver flag
Stop condition Detection



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