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ST7FLCD1 数据表(PDF) 26 Page - STMicroelectronics

部件名 ST7FLCD1
功能描述  8-bit MCU for LCD Monitors with 60 KBytes Flash, 2 KBytes RAM, 2 DDC Ports and Infrared Controller
PDF  95 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7FLCD1 数据表(HTML) 26 Page - STMicroelectronics

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Interrupts
ST7FLCD1
26/95
4.5
Register Description
EXTERNAL INTERRUPT REGISTER (ITRFRE)
Read/Write
Reset value:00h
Bits [7:6] = Reserved. Forced by hardware to 0.
Bit 5 = ITBEDGE Interrupt B Edge Selection.
This bit is set and cleared by software.
0
Falling edge selected on ITB (default)
1
Rising edge selected on ITB
Bit 4 = ITBLAT Falling or Rising Edge Detector Latch.
This bit is set by hardware, when a falling or rising edge, depending on the sensitivity, occurs on the
ITB/PA7 pin. An interrupt is generated if ITBITE = 1. It must be cleared by software.
0
No edge detected on ITB (default)
1
Edge detected on ITB
Bit 3 = ITBITE ITB Interrupt Enable.
This bit is set and cleared by software.
0
ITB interrupt disabled (default)
1
ITB interrupt enabled
Bit 2 = ITAEDGE Interrupt A Edge Selection.
This bit is set and cleared by software.
0
Falling edge selected on ITA (default)
1
Rising edge selected on ITA
Bit 1 = ITALAT Falling or Rising Edge Detector Latch.
This bit is set by hardware when a falling or a rising edge, depending on the sensitivity, occurs on
the ITA/PA6 pin. An interrupt is generated if ITAITE = 1. It must be cleared by software.
0
No edge detected on ITA (default)
1
Edge detected on ITA
Bit 0 = ITAITE ITA Interrupt Enable.
This bit is set and cleared by software.
0
ITA interrupt disabled (default)
1
ITA interrupt enabled
Table 6: External Interrupt Register Map
Address
Reset
Register
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
000Ch
00h
R/W
ITRFRE
0
0
ITB
EDGE
ITBLAT
ITBITE
ITA
EDGE
ITALAT
ITAITE
76
54
321
0
0
0
ITBEDGE
ITBLAT
ITBITE
ITAEDGE
ITALAT
ITAITE



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