ST7FLCD1 datasheet(64/95 Pages) STMICROELECTRONICS

64 / 95 page

Display Data Channel Interfaces (DDC)

ST7FLCD1

64/95

It defines the 256-byte block within the RAM address space containing the data structure. The LSB

is loaded with the data address sent by the master after a write Device Address. It defines the byte

within the data structure currently addressed. It is reset upon entry into the DDC2B mode.

Write Operation

Once the DDC2B Interface has acknowledged a write transfer request, i.e. a Device Address with

RW = 0, it waits for a data address. When the latter is received, it is acknowledged and loaded into

the LSB.

Then, the master may send any number of data bytes that are all acknowledged by the DDC2B

Interface. The data bytes are written in RAM if the WP bit = 0 in the DCR register, otherwise the

RAM location is not modified.

Write operations are always performed in RAM and therefore do not delay DDC transfers.

Meanwhile, concurrent software execution is halted for 2 clock cycles.

Read Operations

All read operations consist of retrieving the data pointed to by an internal address counter which is

initialized by a dummy write and which increments with any read. The DDC2B Interface always

waits for an acknowledge during the 9th bit-time. If the master does not pull the SDA line low during

this bit-time, the DDC2B Interface ends the transfer and switches to a stand-by state.

Current address read: After generating a START condition the master sends a read device

address (RW = 1). The DDC2B Interface acknowledges this and outputs the data byte pointed to by

the internal address pointer which subsequently increments. The master must NOT acknowledge

this byte and must terminate the transfer with a STOP condition.

Figure 36: Mapping of DDC2B Data Structure

Figure 37: Write Sequence

MSB

LSB

Addr Pointer

0000h

FFFFh

128-byte Data

Structure

0000h

FFFFh

128-byte Data

Structure

A0h/A1h

Extended EDID v1 (if present)

Basic EDID v1

LSB :

80h -> FFh

LSB :

00h -> 7Fh

in RAM

Note: Refer to Table 23 for RAM address mapping.

Data Address

Data IN 1

Data IN 2

Data IN n

DEV ADDR

SDA

XXXXh

ADDR

ADDR + n -1

Addr.

Pointer

ADDR + 1

ADDR + n

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