ST7FLCD1 datasheet(71/95 Pages) STMICROELECTRONICS

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ST7FLCD1

Display Data Channel Interfaces (DDC)

Bit 7 = EVF Event flag.

This bit is set by hardware as soon as an event occurs. It is cleared by software by reading the SR2

the interface is disabled (PE = 0).

No event

One of the following events has occurred:

BTF = 1 (Byte received or transmitted)

ADSL = 1 (Either address matched in Slave mode when ACK = 1)

AF = 1 (No acknowledge received after byte transmission if ACK = 1)

STOPF = 1 (Stop condition detected in Slave mode)

BERR = 1 (Bus error, misplaced Start or Stop condition detected)

Bit 6 = Reserved. Forced to 0 by hardware.

Bit 5 = TRA Transmitter/Receiver.

When BTF is set, TRA = 1 if a data byte has been transmitted. It is cleared automatically when BTF

is cleared. It is also cleared by hardware after a Stop condition (STOPF = 1) is detected or when the

interface is disabled (PE = 0).

Data byte received (if BTF = 1)

Data byte transmitted

Bit 4 = BUSY Bus busy.

This bit is set by hardware on detection of a Start condition and cleared by hardware when a Stop

condition is detected. It indicates that a communication is in progress on the bus. This information is

still updated when the interface is disabled (PE = 0).

No communication on the bus

Communication ongoing on the bus

Bit 3 = BTF Byte transfer finished.

This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt

generation if ITE = 1. It is cleared by software by reading the SR1 register followed by a read or a

write to the DR register. It is also cleared by hardware when the interface is disabled (PE = 0).

Following a byte transmission, this bit is set after reception of the acknowledge clock pulse BTF is

cleared by reading the SR1 register followed by writing the next byte in the DR register.

Following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ACK

= 1. BTF is cleared by reading SR1 register followed by reading the byte from DR register.

The SCL line is held low when BTF = 1.

Byte transfer not completed

Byte transfer succeeded

Bit 2 = ADSL Address matched (Slave mode). This bit is set by hardware as soon as the received

slave address matched with the OARx registers content or the DDC/CI address is recognized. An

interrupt is generated if ITE = 1. It is cleared by software by reading the SR1 register or by hardware

when the interface is disabled (PE = 0).

The SCL line is held low when ADSL = 1.

Address mismatched or not received

Received address matched

Bits [1:0] = Reserved. Forced to 0 by hardware.

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