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PC87366 数据表(PDF) 162 Page - National Semiconductor (TI) |
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PC87366 数据表(HTML) 162 Page - National Semiconductor (TI) |
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162 / 240 page ![]() 9.0 Game Port (GMP) (Continued) 162 www.national.com 9.3.5 Game Port Interrupt Enable Register (GMPIEN) This register defines the conditions on which the Game Port asserts its interrupt request signal. This register is functional only in Enhanced mode. Location: Offset 03h Type: R/W Bit 76543210 Name Device B Button 1 IRQ Enable Device B Button 0 IRQ Enable Device A Button 1 IRQ Enable Device A Button 0 IRQ Enable Reserved Position IRQ Event Definition Device B Position IRQ Enable Device A Position IRQ Enable Reset 00000000 Bit Description 7 Device B Button 1 IRQ Enable. When set to 1, the Game Port issues an interrupt request in response to an event triggered by Button 1 of Device B. When set to 0, Button 1 of Device B cannot cause interrupt requests to be issued. 0: Disabled (default) 1: Enabled 6 Device B Button 0 IRQ Enable. Same as bit 7 of this register, but for Device B Button 0. 0: Disabled (default) 1: Enabled 5 Device A Button 1 IRQ Enable. Same as bit 7 of this register, but for Device A Button 1. 0: Disabled (default) 1: Enabled 4 Device A Button 0 IRQ Enable. Same as bit 7 of this register, but for Device A Button 0. 0: Disabled (default) 1: Enabled 3 Reserved 2 Position IRQ Event Definition Defines the event on which the position IRQ is asserted for both game devices. 0: Both X-Position Counter and Y-Position Counter are ready 1: Either X-Position Counter or Y-Position Counter is ready 1 Device B Position IRQ Enable. When set to 1, the Game Port issues an interrupt request when the position reading of Device B is completed and the position counters can be read. When set to 0, no interrupt request is issued in response to any change in the status of Device B position counters. 0: Disabled (default) 1: Enabled 0 Device A Position IRQ Enable. Same as bit 2 of this register, but for Device A. 0: Disabled (default) 1: Enabled |
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