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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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PC87366 数据表(PDF) 165 Page - National Semiconductor (TI) |
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PC87366 数据表(HTML) 165 Page - National Semiconductor (TI) |
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165 / 240 page  9.0 Game Port (GMP) (Continued) 165 www.national.com 9.3.14 Game Port Event Polarity Register (GMPEPOL) This register defines the polarity of button events on which the Game Port issues an interrupt request. This register is functional only in Enhanced mode. Location: Offset 0Ch Type: R/W Bit 76543210 Name Device B Button 1 Event Polarity Device B Button 0 Event Polarity Device A Button 1 Event Polarity Device A Button 0 Event Polarity Reset 00000000 Bit Description 7-6 Device B Button 1 Event Polarity. This bit defines the event polarity on which Device B Button 1 issues an interrupt request. Bits 7 6 Number 0 0 None (default) 0 1 Rising edge 1 0 Falling edge 1 1 Rising and falling edge 5-4 Device B Button 0 Event Polarity. Same as bits 7-6 of this register, but for Device B Button 0. Bits 5 4 Number 0 0 None (default) 0 1 Rising edge 1 0 Falling edge 1 1 Rising and falling edge 3-2 Device A Button 1 Event Polarity. Same as bits 7-6 of this register, but for Device A Button 1. Bits 3 2 Number 0 0 None (default) 0 1 Rising edge 1 0 Falling edge 1 1 Rising and falling edge 1-0 Device A Button 0 Event Polarity. Same as bits 7-6 of this register, but for Device A Button 0. Bits 1 0 Number 0 0 None (default) 0 1 Rising edge 1 0 Falling edge 1 1 Rising and falling edge |
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