PC87366 datasheet(213/240 Pages) NSC

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13.0 Legacy Functional Blocks (Continued)

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13.3 PARALLEL PORT

13.3.1

General Description

The Parallel Port supports all IEEE1284 standard communication modes: Compatibility (known also as Standard or SPP),

Bidirectional (known also as PS/2), FIFO, EPP (known also as Mode 4) and ECP (with an optional Extended ECP mode).

13.3.2

Parallel Port Register Map

The Parallel Port functional block register maps are grouped according to first and second level offsets. EPP and second

level offset registers are available only when base address is 8-byte aligned.

Table 57. Parallel Port Register Map for First Level Offset

First Level

Offset

Mnemonic

Modes (ECR Bits)

765

Type

000h

DATAR

PP Data

000

001

R/W

000h

AFIFO

ECP Address FIFO

0 1 1

001h

DSR

Status

All Modes

002h

DCR

Control

All Modes

R/W

003h

ADDR

EPP Address

1 0 0

R/W

004h

DATA0

EPP Data Port 0

1 0 0

R/W

005h

DATA1

EPP Data Port 1

1 0 0

R/W

006h

DATA2

EPP Data Port 2

1 0 0

R/W

007h

DATA3

EPP Data Port 3

1 0 0

R/W

400h

CFIFO

PP Data FIFO

0 1 0

400h

DFIFO

ECP Data FIFO

0 1 1

R/W

400h

TFIFO

Test FIFO

1 1 0

R/W

400h

CNFGA

Conﬁguration A

1 1 1

401h

CNFGB

Conﬁguration B

1 1 1

402h

ECR

Extended Control

All Modes

R/W

403h

EIR

Extended Index

All Modes

R/W

404h

EDR

Extended Data

All Modes

R/W

405h

EAR

Extended Auxiliary Status

All Modes

R/W

Table 58. Parallel Port Register Map for Second Level Offset

Second Level

Offset

Type

00h

Control0

R/W

02h

Control2

R/W

04h

Control4

R/W

05h

PP Confg0

R/W

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