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PC87366 数据表(PDF) 217 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 PC87366
功能描述  128-Pin LPC SuperI/O with System Hardware Monitoring, MIDI and Game Ports
PDF  240 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

PC87366 数据表(HTML) 217 Page - National Semiconductor (TI)

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13.0 Legacy Functional Blocks (Continued)
217
www.national.com
13.4.3
SP1 and SP2 Register Maps for UART Functionality
.
Table 61. Bank 0 Register Map
Offset
Mnemonic
Register Name
Type
00h
RXD
Receiver Data Port
RO
00h
TXD
Transmitter Data Port
W
01h
IER
Interrupt Enable
R/W
02h
EIR
Event Identification (Read Cycles)
RO
FCR
FIFO Control (Write Cycles)
W
03h
LCRNote 1.
Note 1. When bit 7 of this Register is set to 1, bits 6-0 of BSR select the bank,
as shown in Table 62.
Line Control
R/W
BSRNote 1. Bank Select
04h
MCR
Modem/Mode Control
R/W
05h
LSR
Link Status
RO
06h
MSR
Modem Status
RO
07h
SPR/ASCR Scratchpad/Auxiliary Status and Control
R/W
Table 62. Bank Selection Encoding
BSR Bits
Bank
Selected
Functionality
76543210
0
x
xxxxxx
0
UART + IR
(SP1 + SP2)
1
0
xxxxxx
1
1
1
xxxx
1
x
1
1
1
xxxxx
1
1
11100000
2
11100100
3
11101000
4
IR Only
(SP2)
11101100
5
11110000
6
11110100
7
Table 63. Bank 1 Register Map
Offset
Mnemonic
Register Name
Type
00h
LBGD(L)
Legacy Baud Generator Divisor Port (Low Byte)
R/W
01h
LBGD(H)
Legacy Baud Generator Divisor Port (High Byte)
R/W
02h
Reserved
03h
LCR/BSR
Line Control/Bank Select
R/W
04h - 07h
Reserved



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