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STM8S 数据表(PDF) 56 Page - STMicroelectronics |
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STM8S 数据表(HTML) 56 Page - STMicroelectronics |
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56 / 467 page  Flash program memory and data EEPROM RM0016 56/467 DocID14587 Rev 14 4.8.9 Flash register map and reset values For details on the Flash register boundary addresses, refer to the general hardware register map in the datasheets. Bit 2 EOP: End of programming (write or erase operation) flag This bit is set by hardware. It is cleared by software by reading the register, or when a new write/erase operation starts. 0: No EOP event occurred 1: An EOP operation occurred. An interrupt is generated if the IE bit is set in the FLASH_CR1 register. Bit 1 PUL: Flash Program memory unlocked flag This bit is set by hardware and cleared by software by programming it to 0. 0: Write protection of main Program area enabled 1: Write protection of main Program area has been disabled by writing the correct MASS keys. Bit 0 WR_PG_DIS: Write attempted to protected page flag This bit is set by hardware and cleared by software by reading the register. 0: No WR_PG_DIS event occurred 1: A write attempt to a write protected page occurred. An interrupt is generated if the IE bit is set in the FLASH_CR1 register. Table 7. Flash register map and reset values Address Register name 7654 3 2 1 0 0x00 FLASH_CR1 Reset value - 0 - 0 - 0 - 0 HALT 0 AHALT 0 IE 0 FIX 0 0x01 FLASH_CR2 Reset value OPT 0 WPRG 0 ERASE 0 FPRG 0 - 0 - 0 - 0 PRG 0 0x02 FLASH_NCR2 Reset value NOPT 1 NWPRG 1 NERAS E 1 NFPRG 1 - 1 - 1 - 1 NPRG 1 0x03 FLASH_FPR Reset value - 0 - 0 WPB5 0 WPB4 0 WPB3 0 WPB2 0 WPB1 0 WPB0 0 0x04 FLASH_NFPR Reset value - 1 - 1 NWPB5 1 NWPB4 1 NWPB3 1 NWPB2 1 NWPB1 1 NWPB0 1 0x05 FLASH_IAPSR Reset value - 0 HVOFF 1 - 0 - 0 DUL 0 EOP 0 PUL 0 WR_PG_ DIS 0 0x06- 0x07 Reserved 0x08 FLASH_PUKR Reset value PUK7 0 PUK6 0 PUK5 0 PUK4 0 PUK3 0 PUK2 0 PUK1 0 PUK0 0 0x09 Reserved 0x0A FLASH_DUKR Reset value DUK7 0 DUNP6 0 DUK5 0 DUK4 0 DUK3 0 DUK2 0 DUK1 0 DUK0 0 |
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