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RM0016

Clock control (CLK)

104

9.7

Clock-out capability (CCO)

The configurable Clock Output (CCO) capability allows you to output a clock on the external

CCO pin. You can select one of 6 clock signals as CCO clock:

•

fHSE

•

fHSI

•

fHSIDIV

•

fLSI

•

fMASTER

•

fCPU (with current prescaling selection)

Note:

50% duty cycle is not guaranteed on all possible prescaled values

The selection is controlled by the CCOSEL[3:0] bits in the Configurable clock output register

(CLK_CCOR).

The user has to select first the desired clock for the dedicated I/O pin (see Pin Description

chapter). This I/O must be set at 1 in the corresponding Px_CR1 register to be set as input

with pull-up or push-pull output.

The sequence to really output the chosen clock starts with CCOEN=1 in Configurable clock

output register (CLK_CCOR).

The CCOBSY is set to indicate that the configurable clock output system is operating. As

long as the CCOBSY bit is set, the CCOSEL bits are write protected.

The CCO automatically activates the target oscillator if needed. The CCORDY bit is set

when the chosen clock is ready.

To disable the clock output the user has to clear the CCOEN bit. Both CCOBSY and

CCORDY remain at 1 till the shut down is completed. The time between the clear of CCOEN

and the reset of the two flags can be relatively long, for instance in case the selected clock

output is very slow compared to fCPU.

9.8

CLK interrupts

The following interrupts can be generated by the clock controller:

•

Master clock source switch event

•

Clock Security System event

Both interrupts are individually maskable.

Table 16. CLK interrupt requests

Interrupt event

Event

flag

Enable

control

bit

Exit

from

wait

Exit

from

Halt

CSS event

CSSD

CSSDIE

Yes

Master clock switch event

SWIF

SWIEN

Yes

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