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STM8S 数据表(PDF) 94 Page - STMicroelectronics |
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STM8S 数据表(HTML) 94 Page - STMicroelectronics |
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94 / 467 page  Clock control (CLK) RM0016 94/467 DocID14587 Rev 14 9.9.6 Clock divider register (CLK_CKDIVR) Address offset: 0x06 Reset value: 0x18 7 654 3210 Reserved HSIDIV[1:0] CPUDIV[2:0] r rwrw rw rwrw Bits 7:5 Reserved, must be kept cleared. Bits 4:3 HSIDIV[1:0]: High speed internal clock prescaler These bits are written by software to define the HSI prescaling factor. 00: fHSI= fHSI RC output 01: fHSI= fHSI RC output/2 10: fHSI= fHSI RC output/4 11: fHSI= fHSI RC output/8 Bits 2:0 CPUDIV[2:0]: CPU clock prescaler These bits are written by software to define the CPU clock prescaling factor. 000: fCPU=fMASTER 001: fCPU=fMASTER/2 010: fCPU=fMASTER/4 011: fCPU=fMASTER/8 100: fCPU=fMASTER/16 101: fCPU=fMASTER/32 110: fCPU=fMASTER/64 111: fCPU=fMASTER/128 |
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