STM8S datasheet(98/467 Pages) STMICROELECTRONICS

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Clock control (CLK)

RM0016

98/467

DocID14587 Rev 14

9.9.10

Configurable clock output register (CLK_CCOR)

Address offset: 0x09

Reset value: 0x00

654

3210

Reserved

CCOBSY

CCORDY

CCOSEL[3:0]

CCOEN

rwrw

Bit 7 Reserved, must be kept cleared.

Bit 6 CCOBSY: Configurable clock output busy

This bit is set and cleared by hardware. It indicates that the selected CCO clock source is being

switched-on and stabilized. While CCOBSY is set, the CCOSEL bits are write-protected. CCOBSY

remains set until the CCO clock is enabled.

0: CCO clock not busy

1: CCO clock busy

Bit 5 CCORDY: Configurable clock output ready

This bit is set and cleared by hardware. It indicates that the CCO clock is being output.

0: CCO clock not available

1: CCO clock available

Bits 4:1 CCOSEL[3:0]: Configurable clock output selection.

These bits are written by software to select the source of the output clock available on the

CLK_CCO pin. They are write-protected when CCOBSY is set.

0000: fHSIDIV

0001: fLSI

0010: fHSE

0011: Reserved

0100: fCPU

0101: fCPU/2

0110: fCPU/4

0111: fCPU/8

1000: fCPU/16

1001: fCPU/32

1010: fCPU/64

1011: fHSI

1100: fMASTER

1101: fCPU

1110: fCPU

1111: fCPU

Bit 0 CCOEN: Configurable clock output enable

This bit is set and cleared by software.

0: CCO clock output disabled

1: CCO clock output enabled

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