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STM8S 数据表(PDF) 71 Page - STMicroelectronics |
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STM8S 数据表(HTML) 71 Page - STMicroelectronics |
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71 / 467 page  DocID14587 Rev 14 71/467 RM0016 Interrupt controller (ITC) 72 6.9.4 External interrupt control register 1 (EXTI_CR2) Address offset: 0x01 Reset value: 0x00 7 654 3210 Reserved TLIS PEIS[1:0] rrw rw Bits 7:3 Reserved. Bit 2 TLIS: Top level interrupt sensitivity This bit is set and cleared by software. This bit can be written only when external interrupt is disabled on the corresponding GPIO port (PD7 or PC3, refer to Section 6.6: External interrupts on page 66). 0: Falling edge 1: Rising edge Bits 1:0 PEIS[1:0]: Port E external interrupt sensitivity bits These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3). They define the sensitivity of the Port E external interrupts. 00: Falling edge and low level 01: Rising edge only 10: Falling edge only 11: Rising and falling edge |
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