STM8S datasheet(88/467 Pages) STMICROELECTRONICS

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Clock control (CLK)

RM0016

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DocID14587 Rev 14

9.6

Clock security system (CSS)

The Clock Security System (CSS) monitors HSE crystal clock source failures. When

fMASTER depends on HSE crystal, i.e. when HSE is selected, if the HSE clock fails due to a

broken or disconnected resonator or any other reason, the clock controller activates a stall-

safe recovery mechanism by automatically switching fMASTER to the auxiliary clock source

(HSI/8). Once selected the auxiliary clock source remains enabled until the MCU is reset.

You enable the clock security system by setting the CSSEN bit in the Clock security system

the next reset.

The following conditions must be met so that the CSS can detect HSE quartz crystal

failures:

•

HSE crystal on: (HSEEN = 1 in the External clock register (CLK_ECKR))

•

HSE oscillator in quartz crystal configuration (EXTCLK option bit is reset)

•

CSS function enabled: (CSSEN = 1 in the CLK_CSSR register)

If HSE is the current clock master when a failure is detected, the CSS performs the following

actions:

•

The CSSD bit is set in the CLK_CSSR register and an interrupt is generated if the

CSSIEN bit is set.

•

The Clock master status register (CLK_CMSR), Clock master switch register

(CLK_SWR) register and the HSIDIV[1:0] bits in the Clock divider register

(CLK_CKDIVR) are set to their reset values (CKM[7:0]= SWI[7:0]=E1h). HSI/8

becomes the master clock.

•

The HSIEN bit in the Internal clock register (CLK_ICKR) register is set (HSI on).

•

The HSEEN bit in the External clock register (CLK_ECKR) is cleared (HSE off)

•

The AUX bit is set to indicate that the HSI/8 auxiliary clock source is forced.

You can clear the CSSD bit by software but the AUX bit is cleared only by reset.

To select a faster clock speed, you can modify the HSIDIV[1:0] bits in the CLK_CKDIVR

If HSE is not the current clock master when a failure is detected, the master clock is not

switched to the auxiliary clock and none of the above actions are performed except:

•

The HSEEN bit is cleared in the CLK_ECKR register, HSE is then switched OFF

•

The CSSD bit is set in the CLK_CSSR register and interrupt is generated if CSSDIE is

also set, it can be cleared by software.

If HSE is not the current clock master and the master clock switch to HSE is ongoing, the

SWBSY bit in the CLK_SWCR register must be cleared by software before clearing the

CSSD bit.

If HSE is selected by CCOSEL to be in output mode (see Clock-out capability (CCO)) when

a failure is detected, the selection is automatically changed to force HSI (HSIDIV) instead of

HSE.

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