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STM8S 数据表(PDF) 96 Page - STMicroelectronics |
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STM8S 数据表(HTML) 96 Page - STMicroelectronics |
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96 / 467 page  Clock control (CLK) RM0016 96/467 DocID14587 Rev 14 9.9.8 Peripheral clock gating register 2 (CLK_PCKENR2) Address offset: 0x0A Reset value: 0xFF 7 654 3210 PCKEN2[7:0] rw rw rw rw rw rw rw rw Bits 7:0 PCKEN2[7:0]: Peripheral clock enable These bits are written by software to enable or disable the fMASTER clock to the corresponding peripheral. See Table 17 0: fMASTER to peripheral disabled 1: fMASTER to peripheral enabled Table 18. Peripheral clock gating bits Control bit Peripheral PCKEN27 CAN (product dependent, see datasheet) PCKEN26 Reserved PCKEN25 Reserved PCKEN24 Reserved PCKEN23 ADC PCKEN22 AWU PCKEN21 Reserved PCKEN20 Reserved |
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