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STM8S 数据表(PDF) 27 Page - STMicroelectronics |
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STM8S 数据表(HTML) 27 Page - STMicroelectronics |
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27 / 467 page  DocID14587 Rev 14 27/467 RM0016 Central processing unit (CPU) 28 1.2.2 STM8 CPU register map The CPU registers are mapped in the STM8 address space as shown inTable 2. These registers can only be accessed by the debug module but not by memory access instructions executed in the core. 1.3 Global configuration register (CFG_GCR) 1.3.1 Activation level The MCU activation level is configured by programming the AL bit in the CFG_GCR register. For information on the use of this bit refer to Section 6.4: Activation level/low power mode control on page 63. 1.3.2 SWIM disable By default, after an MCU reset, the SWIM pin is configured to allow communication with an external tool for debugging or Flash/EEPROM programming. This pin can be configured by the application for use as a general purpose I/O. This is done by setting the SWD bit in the CFG_GCR register. Table 2. CPU register map Address offset Register name 765432 1 0 0x00 A MSB ----- - LSB 0x01 PCE MSB - - --- - LSB 0x02 PCH MSB ----- - LSB 0x03 PCL MSB ----- - LSB 0x04 XH MSB ----- - LSB 0x05 XL MSB ----- - LSB 0x06 YH MSB ----- - LSB 0x07 YL MSB ----- - LSB 0x08 SPH MSB ----- - LSB 0x09 SPL MSB ----- - LSB 0x0A CC V 0 I1 H I0 N Z C |
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