STM8S datasheet(97/467 Pages) STMICROELECTRONICS

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RM0016

Clock control (CLK)

104

9.9.9

Clock security system register (CLK_CSSR)

Address offset: 0x08

Reset value: 0x00

654

3210

Reserved

CSSD

CSSDIE

AUX

CSSEN

rrc_w0

rwo

Bits 7:4 Reserved, must be kept cleared.

Bit 3 CSSD: Clock security system detection

This bit is set by hardware and cleared by software writing 0.

0: CSS is off or no HSE crystal clock disturbance detected.

1: HSE crystal clock disturbance detected.

Bit 2 CSSDIE: Clock security system detection interrupt enable

This bit is set and cleared by software.

0: Clock security system interrupt disabled

1: Clock security system interrupt enabled

Bit 1 AUX: Auxiliary oscillator connected to master clock

This bit is set and cleared by hardware.

0: Auxiliary oscillator is off.

1: Auxiliary oscillator (HSI/8) is on and selected as current clock master source.

Bit 0 CSSEN: Clock security system enable

This bit can be read many times and be written once-only by software.

0: Clock security system off

1: Clock security system on

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