STM8S datasheet(86/467 Pages) STMICROELECTRONICS

部件名	STM8S

功能描述	STM8S Series and STM8AF Series 8-bit microcontrollers

PDF	467 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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86 / 467 page

Clock control (CLK)

RM0016

86/467

DocID14587 Rev 14

Figure 23. Clock switching flowchart (manual mode example)

9.3

Low-speed clock selection

The Low-speed clock source for the AWU or the independent watchdog can be LSI or HSE

divided according to the CKAWUSEL option bit. Refer to option bytes section in the

datasheet.

The division factor for HSE has to be programmed in the HSEPRSC[1:0] option bits Refer to

in the option bytes section of the datasheet. The goal is to get 128 kHz at the output of the

HSE prescaler.

9.4

CPU clock-divider

The CPU clock (fCPU) is derived from the master clock (fMASTER), divided by a factor

programmed in the CPUDIV[2:0] bits in the Clock divider register (CLK_CKDIVR). Seven

division factors (1 to 128 in steps of power of 2) can be selected (refer to Figure 20).

The fCPU signal is the clock for both the CPU and the window watchdog.

STM8S 数据表(PDF) 86 Page - STMicroelectronics