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STM8S 数据表(PDF) 19 Page - STMicroelectronics

部件名 STM8S
功能描述  STM8S Series and STM8AF Series 8-bit microcontrollers
PDF  467 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM8S 数据表(HTML) 19 Page - STMicroelectronics

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22
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Figure 1.
Programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 2.
Stacking order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 3.
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 4.
Default stack model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 5.
Customized stack model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 6.
Flash memory and data EEPROM organization on low density STM8S and STM8AF . . . 38
Figure 7.
Flash memory and data EEPROM organization on medium density STM8S and STM8AF39
Figure 8.
Flash memory and data EEPROM organization high density STM8S and STM8AF . . . . . 40
Figure 9.
UBC area size definition on low density STM8S devices . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 10.
UBC area size definition on medium density STM8S
and STM8AF with up to 32 Kbytes of Flash program memory . . . . . . . . . . . . . . . . . . . . . . 42
Figure 11.
UBC area size definition on high density STM8S and
STM8AF with up to 128 Kbytes of Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 12.
SWIM pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 13.
Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 14.
Priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 15.
Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 16.
Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 17.
Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 18.
Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 19.
VDD/VDDIO voltage detection: POR/BOR threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 20.
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 21.
HSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 22.
Clock switching flowchart (automatic mode example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 23.
Clock switching flowchart (manual mode example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 24.
GPIO block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 25.
AWU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 26.
Beep block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 27.
Independent watchdog (IWDG) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 28.
Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 29.
Approximate timeout duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 30.
Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 31.
TIM1 general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 32.
Time base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 33.
16-bit read sequence for the counter (TIM1_CNTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 34.
Counter in up-counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 35.
Counter update when ARPE = 0 (ARR not preloaded) with prescaler = 2 . . . . . . . . . . . . 144
Figure 36.
Counter update event when ARPE = 1 (TIM1_ARR preloaded). . . . . . . . . . . . . . . . . . . . 144
Figure 37.
Counter in down-counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 38.
Counter update when ARPE = 0 (ARR not preloaded) with prescaler = 2 . . . . . . . . . . . . 146
Figure 39.
Counter update when ARPE = 1 (ARR preloaded), with prescaler = 1 . . . . . . . . . . . . . . 146
Figure 40.
Counter in center-aligned mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 41.
Counter timing diagram, fCK_CNT = fCK_PSC, TIM1_ARR = 06h, ARPE = 1 . . . . . . . . . . . 148
Figure 42.
Update rate examples depending on mode and TIM1_RCR register settings . . . . . . . . . 150
Figure 43.
Clock/trigger controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 44.
Control circuit in normal mode, fCK_PSC = fMASTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 45.
TI2 external clock connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 46.
Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153



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