STM8S datasheet(92/467 Pages) STMICROELECTRONICS

92 / 467 page

Clock control (CLK)

RM0016

92/467

DocID14587 Rev 14

9.9.3

Clock master status register (CLK_CMSR)

Address offset:0x03

Reset value: 0xE1

9.9.4

Clock master switch register (CLK_SWR)

Address offset: 0x04

Reset value: 0xE1

654

3210

CKM[7:0]

rrr

rrrr

Bits 7:0 CKM[7:0]: Clock master status bits

These bits are set and cleared by hardware. They indicate the currently selected master clock

source. An invalid value occurring in this register will automatically generate an MCU reset.

0xE1: HSI selected as master clock source (reset value)

0xD2: LSI selected as master clock source (only if LSI_EN option bit is set)

0xB4: HSE selected as master clock source

654

3210

SWI[7:0]

Bits 7:0 SWI[7:0]: Clock master selection bits

These bits are written by software to select the master clock source. Its contents are write protected

while a clock switch is ongoing (while the SWBSY bit is set). They are set to the reset value (HSI) if

the AUX bit is set in the CLK_CSSR register. If Fast Halt wakeup mode is selected (FHW bit =1 in

CLK_ICKR register) then these bits are set by hardware to E1h (HSI selected) when resuming from

Halt/Active-halt mode.

0xE1: HSI selected as master clock source (reset value)

0xD2: LSI selected as master clock source (only if LSI_EN option bit is set)

0xB4: HSE selected as master clock source

STM8S 数据表(PDF) 92 Page - STMicroelectronics

STM8S 数据表(HTML) 92 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载