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STM8S 数据表(PDF) 20 Page - STMicroelectronics

部件名 STM8S
功能描述  STM8S Series and STM8AF Series 8-bit microcontrollers
PDF  467 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM8S 数据表(HTML) 20 Page - STMicroelectronics

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List of figures
RM0016
20/467
DocID14587 Rev 14
Figure 47.
External trigger input block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 48.
Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 49.
Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 50.
Control circuit in trigger reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 51.
Control circuit in trigger gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 52.
Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 53.
Timer chaining system implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 54.
Trigger/master mode selection blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 55.
Master/slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 56.
Gating timer B with OC1REF of timer A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 57.
Gating timer B with the counter enable signal of timer A (CNT_EN) . . . . . . . . . . . . . . . . 163
Figure 58.
Triggering timer B with the UEV of timer A (TIMERA-UEV) . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 59.
Triggering timer B with counter enable CNT_EN of timer A . . . . . . . . . . . . . . . . . . . . . . 165
Figure 60.
Triggering Timer A and B with Timer A TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 61.
Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 62.
16-bit read sequence for the TIM1_CCRi register in capture mode . . . . . . . . . . . . . . . . . 167
Figure 63.
Channel input stage block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 64.
Input stage of TIM 1 channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 65.
PWM input signal measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 66.
PWM input signal measurement example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 67.
Channel output stage block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 68.
Detailed output stage of channel with complementary output (channel 1) . . . . . . . . . . . . 172
Figure 69.
Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 70.
Edge-aligned counting mode PWM mode 1 waveforms (ARR = 8) . . . . . . . . . . . . . . . . . 175
Figure 71.
Center-aligned PWM waveforms (ARR = 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 72.
Example of one-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 73.
Complementary output with deadtime insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 74.
Deadtime waveforms with a delay greater than the negative pulse . . . . . . . . . . . . . . . . . 179
Figure 75.
Deadtime waveforms with a delay greater than the positive pulse . . . . . . . . . . . . . . . . . . 179
Figure 76.
Six-step generation, COM example (OSSR = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 77.
Behavior of outputs in response to a break (channel without complementary output) . . . 182
Figure 78.
Behavior of outputs in response to a break (TIM1 complementary outputs) . . . . . . . . . . 183
Figure 79.
ETR activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 80.
Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 81.
Example of encoder interface mode with IC1 polarity inverted. . . . . . . . . . . . . . . . . . . . . 186
Figure 82.
TIM2/TIM3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 83.
TIM5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 84.
Time base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 85.
Input stage block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 86.
Input stage of TIM 2 channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 87.
Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 88.
Output stage of channel 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 89.
TIM4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Figure 90.
TIM6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Figure 91.
SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Figure 92.
Single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Figure 93.
Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Figure 94.
TXE/RXNE/BSY behavior in full duplex mode (RXONLY = 0).
Case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Figure 95.
TXE/RXNE/BSY behavior in slave / full duplex mode
(BDM = 0, RXONLY = 0). Case of continuous transfers. . . . . . . . . . . . . . . . . . . . . . . . . . 271
Figure 96.
TXE/BSY in master transmit-only mode



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