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STM8S 数据表(PDF) 78 Page - STMicroelectronics |
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STM8S 数据表(HTML) 78 Page - STMicroelectronics |
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78 / 467 page  Clock control (CLK) RM0016 78/467 DocID14587 Rev 14 9 Clock control (CLK) The clock controller is designed to be powerful, very robust, and at the same time easy to use. Its purpose is to allow you to obtain the best performance in your application while at the same time get the full benefit of all the microcontroller’s power saving capabilities. You can manage all the different clock sources independently and distribute them to the CPU and to the various peripherals. Prescalers are available for the master and CPU clocks. A safe and glitch-free switch mechanism allows you to switch the master clock on the fly from one clock source to another one. EMC-hardened clock configuration registers To protect the application against spurious write access or system hang-up, possibly caused by electromagnetic disturbance, the most critical CLK registers are implemented as two bitfields that must contain complementary values. Mismatches are automatically detected by the CLK, triggering an EMC reset and allowing the application to cleanly recover normal operations. See CLK register description for more details. |
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