STM8S datasheet(82/467 Pages) STMICROELECTRONICS

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Clock control (CLK)

RM0016

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DocID14587 Rev 14

Fast wakeup feature

If the FHWU bit in the Internal clock register (CLK_ICKR) is set, this automatically selects

the HSI clock as master clock after MCU wakeup from Halt or Active-halt (see Low power

chapter).

Calibration

Each device is factory calibrated by ST.

After reset, the factory calibration value is automatically loaded in an internal calibration

If the application is subject to voltage or temperature variations this may affect the RC

oscillator speed. You can trim the HSI frequency in the application using the HSI clock

calibration trimming register (CLK_HSITRIMR). In this register there are 3 or 4 bits providing

an additional trimming value that is added to the internal HSI calibration register value.

The width of the trimming steps with 4 bits is half the trimming step width with 3 bits.

As the trimming step width depends on the absolute frequency of the RC oscillator, a

successive approximation method needs to be applied for the trimming. This method is

described in a separate technical document.

9.1.3

LSI

The 128 kHz LSI RC acts as a low power, low cost alternative master clock source as well

as a low power clock source that can be kept running in Halt mode for the independent

watchdog (IWDG) and auto-wakeup unit (AWU).

Table 14. Devices with 4 trimming bits

Trimming bits value

Trimming steps

Trimming bits value

Trimming steps

0111b

1111b

-1

0110b

1110b

-2

0101b

1101b

-3

0100b

1100b

-4

0011b

1011b

-5

0010b

1010b

-6

0001b

1001b

-7

0000b

1000b

-8

Table 15. Devices with 3 trimming bits

Trimming bits value

Trimming steps

Trimming bits value

Trimming steps

011b

111b

-1

010b

110b

-2

001b

101b

-3

000b

100b

-4

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