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STM8S 数据表(PDF) 102 Page - STMicroelectronics

部件名 STM8S
功能描述  STM8S Series and STM8AF Series 8-bit microcontrollers
PDF  467 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM8S 数据表(HTML) 102 Page - STMicroelectronics

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Power management
RM0016
102/467
DocID14587 Rev 14
10.1.1
Clock management for low consumption
Slowing down the system clock
In Run mode, choosing the oscillator to be used as the system clock source is very
important to ensure the best compromise between performance and consumption. The
selection is done by programming the clock controller registers. Refer to the Clock control
(CLK) section.
As a further measure, fCPU can be reduced by writing to the CPUDIV[2:0] bits in the Clock
divider register (CLK_CKDIVR). This reduces the speed of the CPU and consequently the
power consumption of the MCU. The other peripherals (clocked by fMASTER) are not affected
by this setting.
To return to full speed at any time in Run mode, clear the CPUDIV[2:0] bits.
Peripheral clock gating
For additional power saving you can use peripheral clock gating (PCG). This can be done at
any time by selectively enabling or disabling the fMASTER clock connection to individual
peripherals. Refer to the Clock control (CLK) section.
These settings are effective in both Run and Wait modes.
10.2
Low power modes
The main characteristics of the four low power modes are summarized in Table 20.
Table 20. Low power mode management
Mode
(consumption
level)
Main voltage
regulator
Oscillators
CPU
Peripherals
Wakeup trigger
event
Wait
( - )
On
On
Off
On(1)
All internal interrupts
(including AWU) or
external interrupts,
reset
Active-halt
( - - )
On
Off
except LSI (or
HSE)
Off
Only AWU(2)
AWU or external(3)
interrupts, reset
Active-halt with
MVR auto power off
( - - - )
Off
(low power
regulator on)
Off
except LSI only
Off
Only AWU(2)
AWU or external(3)
interrupts, reset
Halt
( - - - - )
Off
(low power
regulator on)
Off
Off
Off(2)
External(3) interrupts,
reset
1. If the peripheral clock is not disabled by peripheral clock gating function.
2. If activated, BEEP or IWDG stay switched on. In this case, the LSI clock is forced to run.
3. Including communication peripheral interrupts.



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