STM8S datasheet(103/467 Pages) STMICROELECTRONICS

103 / 467 page

DocID14587 Rev 14

103/467

RM0016

Power management

104

10.2.1

Wait mode

Wait mode is entered from Run mode by executing a WFI (wait for interrupt) instruction: this

stops the CPU but allows the other peripherals and interrupt controller to continue to run.

Therefore the consumption decreases accordingly. Wait mode can be combined with PCG

(peripheral clock gating), reduced CPU clock frequency and low mode clock source

selection (LSI, HSI) to further reduce the power consumption of the device. Refer to the

Clock control (CLK) description.

In Wait mode, all the registers and RAM contents are preserved, the previously defined

clock configuration remains unchanged (Clock master status register (CLK_CMSR)).

When an internal or external interrupt request occurs, the CPU wakes-up from Wait mode

and resumes processing.

10.2.2

Halt mode

In this mode the master clock is stopped. This means that the CPU and all the peripherals

clocked by fMASTER or by derived clocks are disabled. As a result, none of the peripherals

are clocked and the digital part of the MCU consumes almost no power.

In Halt mode, all the registers and RAM contents are preserved, by default the clock

configuration remains unchanged (Clock master status register (CLK_CMSR)).

The MCU enters Halt mode when a HALT instruction is executed. Wakeup from Halt mode

is triggered by an external interrupt, sourced by a GPIO port configured as interrupt input or

an Alternate Function pin capable of triggering a peripheral interrupt.

In this mode the MVR regulator is switched off to save power. Only the LPVR regulator (and

brown-out reset) is active.

Fast clock wakeup

The HSI RC start-up time is much faster than the HSE crystal start-up time (refer to the

Electrical Parameters in the datasheet). Therefore, to optimize the MCU wakeup time, it is

recommended to select the HSI clock as the fMASTER clock source before entering Halt

mode.

This selection can be done without clock switching using the FHWU bit in the Internal clock

10.2.3

Active-halt modes

Active-halt mode is similar to Halt mode except that it does not require an external interrupt

for wakeup. It uses the AWU to generate a wakeup event internally after a programmable

delay.

In Active-halt mode, the main oscillator, the CPU and almost all the peripherals are stopped.

Only the LSI RC or HSE oscillators are running to drive the AWU counters and IWD counter

if enabled.

To enter Active-halt mode, first enable the AWU as described in the AWU section. Then

execute a HALT instruction.

STM8S 数据表(PDF) 103 Page - STMicroelectronics

STM8S 数据表(HTML) 103 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载