 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
STM8S 数据表(PDF) 184 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STM8S 数据表(HTML) 184 Page - STMicroelectronics |
|
|
184 / 467 page  16-bit advanced control timer (TIM1) RM0016 184/467 DocID14587 Rev 14 17.5.9 Clearing the OCiREF signal on an external event The OCiREF signal of a given channel can be cleared when a high level is detected on ETRF (if OCiCE =1 in the TIM1_CCMRi registers, one enable bit per channel). The OCiREF signal remains low until the next UEV occurs. This function can be used in output compare mode and PWM mode only. It does not work in forced mode. The OCiREF signal can be connected to the output of a comparator and be used for current handling by configuring the external trigger as follows: 1. Switch off the external trigger prescaler by setting bits ETPS[1:0] in the TIM1_ETR register to 00. 2. Disable external clock mode 2 by setting the ECE bit in the TIM1_ETR register to 0 3. Configure the external trigger polarity (ETP) and the external trigger filter (ETF) as desired. Refer to Figure 47: External trigger input block diagram. Figure 79 shows the behavior of the OCiREF signal when the ETRF input becomes high, for both values of the enable bits OCiCE. In this example, the timer is programmed in PWM mode. Figure 79. ETR activation |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
