ZUSBOPTSC01ZAC datasheet(109/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

PWM Output Control Register

Z8FMC16100 Series Flash MCU

Product Specification

PWM Output Control Register

The PWM Output Control (PWMOUT) Register, shown in Table 56, enables modulator

control of the six PWM output signals. Output control is enabled by the OUTCTL bit in

the PWMCTL0 register. The Pulse-Width Modulator continues to operate, but has no

effect on the disabled PWM pins. If a fault condition is detected all PWM outputs are

forced to their selected OFF state.

Current Sense ADC Trigger Control Register

An ADC trigger is generated when the PWM output signals match the state specified by

the Current-Sense ADC-Trigger control register. The match logic is an AND-OR tree that

will solve to true if based on the register settings. An ADC conversion will be triggered on

the rising edge of this signal. The logic equation for the adc-trigger is:

ADCTRIGGER = CSTPOL ^ (

( HEN & PWM0H &PWM1H & PWM2H) |

( LEN & PWM0L &PWM1L & PWM2L) |

( nHEN & !PWM0H &!PWM1H & !PWM2H) |

( nLEN & !PWM0H & !PWM1H & !PWM2H) )

Table 56. PWM Output Control Register (PWMOUT)

BITS

FIELD

Reserved Reserved

OUT2L

OUT2H

OUT1L

OUT1H

OUT0L

OUT0H

RESET

R/W

ADDR

F27H

Bit

Position

Value

(H)

Description

[7,6]

Reserved

Must be 0.

[5, 3, 1]

OUT2L/

OUT1L/

OUT0L

PWM 2L/1L/0L Output Configuration

PWM 2L/1L/0L output signal is enabled and controlled by PWM.

PWM 2L/1L/0L output signal is in low-side off-state.

[4, 2, 0]

OUT2H/

OUT1H/

OUT0H

PWM 2H/1H/0H Output Configuration

PWM 2H/1H/0H output signal is enabled and controlled by PWM.

PWM 2H/1H/0H output signal is in high-side off-state.

ZUSBOPTSC01ZAC 数据表(PDF) 109 Page - Zilog, Inc.

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