ZUSBOPTSC01ZAC datasheet(268/402 Pages) ZILOG

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On-Chip Debugger

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!® Motor Control Flash MCUs

Product Specification

246

abled during critical sections of code where interrupts do not occur (such as adjusting the

stack pointer or modifying shared data).

Host software can poll the IDLE bit of the OCDSTAT register to determine if the OCD is

looping on a BRK instruction. When software wants to stop the CPU on the BRK instruc-

tion on which it is looping, software must not set the DBGMODE bit of the OCDCTL reg-

ister. The CPU may have vectored to an interrupt service routine. Instead, software clears

the BRKLP bit. This allows the CPU to finish the interrupt service routine it may be in and

return to the BRK instruction. When the CPU returns to the BRK instruction on which it

was previously looping, it automatically sets the DBGMODE bit and enters DEBUG

mode.

The majority of the OCD commands remain disabled when the eZ8 CPU is looping on a

BRK instruction. The eZ8 CPU must be in DEBUG mode before these commands can be

issued.

Break Points in Flash Memory

The BRK instruction is Op Code 00h, which corresponds to the fully programmed state of

a byte in Flash memory. To implement a break point, write 00h to the appropriate address,

overwriting the current instruction. To remove a break point, erase the corresponding page

of Flash memory and reprogram with the original data.

OCDCNTR Register

The On-Chip Debugger contains a multipurpose 16-bit Counter Register. It can be used

for the following:

• Count system clock cycles between break points

• Generate a BRK when it counts down to 0

• Generate a BRK when its value matches the Program Counter

When configured as a counter, the OCDCNTR register starts counting when the On-Chip

Debugger leaves DEBUG mode and stops counting when it enters DEBUG mode again or

when it reaches the maximum count of FFFFh. The OCDCNTR register automatically

resets itself to 0000h when the OCD exits DEBUG mode if it is configured to count clock

cycles between break points.

If the OCDCNTR Register is configured to generate a BRK when it counts down to zero,

it will not be reset when the CPU starts running. The counter will start counting down

toward zero once the On-Chip debugger leaves DEBUG mode. If the On-Chip Debugger

enters DEBUG mode before the OCDCNTR register counts down to zero, the OCDCNTR

will stop counting.

If the OCDCNTR register is configured to generate a BRK when the program counter

matches the OCDCNTR register, the OCDCNTR register will not be reset when the CPU

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