ZUSBOPTSC01ZAC datasheet(267/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

Automatic Reset

Z8FMC16100 Series Flash MCU

Product Specification

245

• Transmit Collision (OCD and host simultaneous transmission detected by the OCD)

When the OCD detects one of these errors, it aborts any command currently in progress,

transmits a Serial Break 4096 system clock cycles long back to the host, and resets the

Auto-Baud Detector/Generator. A Framing Error or Transmit Collision can be caused by

the host sending a Serial Break to the OCD. Because of the open-drain nature of the inter-

face, returning a Serial Break break back to the host only extends the length of the Serial

Break if the host releases the Serial Break early.

The host transmits a Serial Break on the DBG pin when first connecting to the

Z8FMC16100 Series Flash MCU device or when recovering from an error. A Serial Break

from the host resets the Auto-Baud Generator/Detector but does not reset the OCD Con-

trol Register. A Serial Break leaves the device in DEBUG mode if that is the current mode.

The OCD is held in Reset until the end of the Serial Break when the DBG pin returns

High. Because of the open-drain nature of the DBG pin, the host can send a Serial Break to

the OCD even if the OCD is transmitting a character.

Automatic Reset

The Z8FMC16100 Series Flash MCU devices have the capability to switch clock sources

during operation. If the Auto-Baud is set and the clock source is switched, the Auto-Baud

value becomes invalid. A new Auto-Baud value must be configured with the new clock

frequency.

The oscillator control logic has clock switch detection. If a clock switch is detected and

the Auto-Baud is set, the device will automatically send a Serial Break for 4096 clocks.

This will reset the Auto-Baud and indicate to the host that a new Auto-Baud character

should be sent.

Break Points

Execution break points are generated using the BRK instruction (Op Code 00h). When the

eZ8 CPU decodes a BRK instruction, it signals the On-Chip Debugger. If break points are

enabled, the OCD idles the eZ8 CPU and enters DEBUG mode. If break points are not

enabled, the OCD ignores the BRK signal and the BRK instruction operates as a NOP

instruction.

If break points are enabled, the OCD can be configured to automatically enter DEBUG

mode, or to loop on the break instruction. If the OCD is configured to loop on the BRK

instruction, then the CPU remains able to service DMA and interrupt requests.

The loop on BRK instruction can service interrupts in the background. For interrupts to be

serviced in the background, there cannot be any break points in the interrupt service rou-

tine. Otherwise, the CPU stops on the break point in the interrupt routine. For interrupts to

be serviced in the background, interrupts must also be enabled. Debugging software does

not automatically enable interrupts when using this feature. Interrupts are typically dis-

ZUSBOPTSC01ZAC 数据表(PDF) 267 Page - Zilog, Inc.

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