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ZUSBOPTSC01ZAC 数据表(PDF) 295 Page - Zilog, Inc. |
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ZUSBOPTSC01ZAC 数据表(HTML) 295 Page - Zilog, Inc. |
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295 / 402 page ![]() PS024604-1005 P R E L I M I N A R Y On-Chip Debugger Timing Z8FMC16100 Series Flash MCU Product Specification 273 On-Chip Debugger Timing Figure 53 and Table 151 provide timing information for the DBG pin. The DBG pin tim- ing specifications assume a 4µs maximum rise and fall time. Figure 53. On-Chip Debugger Timing Table 151. On-Chip Debugger Timing Parameter Abbreviation Delay (ns) Minimum Maximum T1 XIN Rise to DBG Valid Delay — 15 T2 XIN Rise to DBG Output Hold Time 2 — T3 DBG to XIN Rise Input Setup Time 10 — T4 DBG to XIN Rise Input Hold Time 5 — DBG Frequency System Clock ÷ 4 TCLK XIN DBG Output Output Data T1 T2 DBG Input Input Data T4 T3 |
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