ZUSBOPTSC01ZAC datasheet(296/402 Pages) ZILOG

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Electrical Characteristics

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!® Motor Control Flash MCUs

Product Specification

274

UART Timing

Figure 54 and Table 152 provide timing information for UART pins for the case where the

Clear To Send input pin (CTS) is used for flow control. In this example, it is assumed that

the Driver Enable polarity has been configured to be Active Low and is represented here

by DE. The CTS to DE assertion delay (T1) assumes the UART Transmit Data Register

has been loaded with data prior to CTS assertion.

Figure 54. UART Timing with CTS

Table 152. UART Timing with CTS

Parameter

Abbreviation

Delay (ns)

Minimum

Maximum

CTS fall to DE assertion delay

2 x XIN period 2 x XIN period

+ 1 bit period

DE assertion to TxD falling edge (start)

delay

1 bit period

1 bit period +

1 x XIN period

End of stop bit(s) to DE deassertion delay 1 x XIN period 2 x XIN period

End of

Stop Bit(s)

CTS

(Input)

(Output)

TxD

(Output)

Bit 0

Bit 1

Bit 7

Stop

Parity

Start

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