ZUSBOPTSC01ZAC datasheet(300/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

eZ8 CPU Instruction Set

Z8 Encore!® Motor Control Flash MCUs

Product Specification

278

Assembly Language Syntax

For proper instruction execution, eZ8 CPU assembly language syntax requires that the

operands be written as ‘destination, source’. After assembly, the object code usually has

the operands in the order ’source, destination’, but ordering is Op Code-dependent. The

following instruction examples illustrate the format of some basic assembly instructions

and the resulting object code produced by the assembler. This binary format must be fol-

lowed by users that prefer manual program coding or intend to implement their own

assembler.

Example 1.

If the contents of registers 43h and 08h are added and the result is stored in

43h

, the assembly syntax and resulting object code is:

Example 2.

In general, when an instruction format requires an 8-bit register address, that

address can specify any register location in the range 0–255 or, using Escaped Mode

Addressing in working registers R0–R15. If the contents of Register 43h and Working

object code is:

; Working Register R7, is the source. The contents

of R7 is

; written into R4.

LD 234H, #%01

; Another Load (LD) instruction with two operands.

; The first operand, Extended Mode Register Address

234H,

; identifies the destination. The second operand,

Immediate Data

; value 01h, is the source. The value 01h is

written into the

; Register at address 234h.

Assembly Language Code

ADD

43H,

08h

(ADD dst, src)

Object Code

(OPC src, dst)

Assembly Language Code

ADD

43H,

(ADD dst, src)

Object Code

(OPC src, dst)

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