ZUSBOPTSC01ZAC datasheet(301/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

eZ8 CPU Instruction Set

Z8FMC16100 Series Flash MCU

Product Specification

279

The size of the register file varies depending upon device type. The register file is 512

bytes for the Z8FMC16100 Series Flash MCU.

eZ8 CPU Instruction Notation

In the eZ8 CPU Instruction Summary and Description sections, the operands, condition

codes, status flags, and address modes are represented by a notational shorthand that is

described in Table 154.

Table 154. Notational Shorthand

Notation Description

Operand Range

Bit

b represents a value from 0 to 7 (000b to 111b).

Condition Code

—

See Condition Codes overview in the eZ8 CPU

User Manual (UM0128).

Direct Address

Addrs

Addrs represents a number in the range of 0000h

to FFFFh.

Extended Addressing Register Reg

Reg. represents a number in the range of 000h to

FFFh.

Immediate Data

#Data

Data is a number between 00h to FFh.

Indirect Working Register

@Rn

n = 0 –15.

Indirect Register

@Reg

Reg. represents a number in the range of 00h to

FFh.

Irr

Indirect Working Register Pair

@RRp

p = 0, 2, 4, 6, 8, 10, 12, or 14.

IRR

Indirect Register Pair

@Reg

Reg. represents an even number in the range 00h

to FEh.

Polarity

Polarity is a single bit binary value of either 0b or

1b.

Working Register

n = 0–15.

Reg

Reg. represents a number in the range of 00h to

FFh.

Relative Address

X represents an index in the range of +127 to

–128, which is an offset relative to the address of

the next instruction.

Working Register Pair

RRp

p = 0, 2, 4, 6, 8, 10, 12, or 14.

Reg

Reg. represents an even number in the range of

00h to FEh.

Note:

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