ZUSBOPTSC01ZAC datasheet(317/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

eZ8 CPU Instruction Set

Z8FMC16100 Series Flash MCU

Product Specification

295

Flags Register

The Flags Register contains the status information regarding the most recent arithmetic,

logical, bit manipulation or rotate and shift operation. The Flags Register contains six bits

of status information that are set or cleared by CPU operations. Four of the bits (C, V, Z,

and S) can be tested for use with conditional jump instructions. Two flags (H and D) can-

not be tested and are used for Binary-Coded Decimal (BCD) arithmetic.

The two remaining bits, User Flags (F1 and F2), are available as general-purpose status

bits. User Flags are unaffected by arithmetic operations and must be set or cleared by

instructions. The User Flags cannot be used with conditional Jumps. They are undefined at

TMX dst, src

dst AND src

ER ER

— *

0 — —

TRAP Vector

← SP – 2

@SP

← PC

← SP – 1

@SP

← FLAGS

← @Vector

Vect

— ——— ——

WDT

— ——— ——

XOR dst, src

dst

← dst XOR src

— *

0 — —

rIr

RIR

RIM

XORX dst, src

dst

← dst XOR src

ER ER

— *

0 — —

Table 165. eZ8 CPU Instruction Summary (Continued)

Assembly

Mnemonic

Symbolic Operation

Address

Mode

Code(s)

(Hex)

Flags

Fetch

Cycles

Instr.

Cycles

dst src

C Z S V D H

Note: Flags Notation:

* = Value is a function of the result of the operation.

– = unaffected.

X = undefined.

0 = reset to 0.

1 = set to 1.

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