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ZUSBOPTSC01ZAC 数据表(PDF) 317 Page - Zilog, Inc.

部件名 ZUSBOPTSC01ZAC
功能描述  Z8 Encore-R Motor Control Flash MCUs
PDF  402 Pages
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制造商  ZILOG [Zilog, Inc.]
网页  http://www.zilog.com
标志 ZILOG - Zilog, Inc.

ZUSBOPTSC01ZAC 数据表(HTML) 317 Page - Zilog, Inc.

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PS024604-1005
P R E L I M I N A R Y
eZ8 CPU Instruction Set
Z8FMC16100 Series Flash MCU
Product Specification
295
Flags Register
The Flags Register contains the status information regarding the most recent arithmetic,
logical, bit manipulation or rotate and shift operation. The Flags Register contains six bits
of status information that are set or cleared by CPU operations. Four of the bits (C, V, Z,
and S) can be tested for use with conditional jump instructions. Two flags (H and D) can-
not be tested and are used for Binary-Coded Decimal (BCD) arithmetic.
The two remaining bits, User Flags (F1 and F2), are available as general-purpose status
bits. User Flags are unaffected by arithmetic operations and must be set or cleared by
instructions. The User Flags cannot be used with conditional Jumps. They are undefined at
TMX dst, src
dst AND src
ER ER
78
— *
*
0 — —
4
3
ER
IM
79
4
3
TRAP Vector
SP
← SP – 2
@SP
← PC
SP
← SP – 1
@SP
← FLAGS
PC
← @Vector
Vect
or
F2
— ——— ——
2
6
WDT
5F
— ——— ——
1
2
XOR dst, src
dst
← dst XOR src
r
r
B2
— *
*
0 — —
2
3
rIr
B3
2
4
RR
B4
3
3
RIR
B5
3
4
RIM
B6
3
3
IR
IM
B7
3
4
XORX dst, src
dst
← dst XOR src
ER ER
B8
— *
*
0 — —
4
3
ER
IM
B9
4
3
Table 165. eZ8 CPU Instruction Summary (Continued)
Assembly
Mnemonic
Symbolic Operation
Address
Mode
Op
Code(s)
(Hex)
Flags
Fetch
Cycles
Instr.
Cycles
dst src
C Z S V D H
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.



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