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ZUSBOPTSC01ZAC 数据表(PDF) 339 Page - Zilog, Inc.

部件名 ZUSBOPTSC01ZAC
功能描述  Z8 Encore-R Motor Control Flash MCUs
PDF  402 Pages
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制造商  ZILOG [Zilog, Inc.]
网页  http://www.zilog.com
标志 ZILOG - Zilog, Inc.

ZUSBOPTSC01ZAC 数据表(HTML) 339 Page - Zilog, Inc.

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PS024604-1005
P R E L I M I N A R Y
Appendix A—Register Tables
Z8FMC16100 Series Flash MCU
Product Specification
317
Hex Address: F21
PWM Control 1 Register (PWMCTL1)
BITS
7
6
5
4
3
2
1
0
FIELD
RLFREQ[1:0]
INDEN
Pol45
Pol23
Pol10
PRES[1:0]
RESET
00
0
0
00
00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
F21H
Bit
Position
Value
(H)
Description
[7:6]
RLFREQ[1:0]
00
01
10
11
Reload Event Frequency
This bit field is buffered. Changes to the reload event frequency takes effect at
the end of the current PWM period. Reads always return the bit values from the
temporary holding register.
PWM reload event occurs at the end of every PWM period.
PWM reload event occurs once every 2 PWM periods.
PWM reload event occurs once every 4 PWM periods.
PWM reload event occurs once every 8 PWM periods.
[5]
INDEN
0
Independent PWM Mode Enable
This bit may only be altered when PWEN (PWMCTL0) cleared.
PWM outputs operate as 3 complementary pairs.
1
PWM outputs operate as 6 independent channels.
[4]
Pol2
1
Invert Output polarity for channel pair PWM2.
0
Non-inverted polarity for channel pair PWM2.
[3]
Pol1
1
Invert Output polarity for channel pair PWM1.
0
Non-inverted polarity for channel pair PWM1.
[2]
Pol0
1
Invert Output polarity for channel pair PWM0.
0
Non-inverted polarity for channel pair PWM0.
[1:0]
PRES
00
01
10
11
PWM Prescaler
The prescaler divides down the PWM input clock (either the system clock or the
PWMIN external input). This field is buffered. Changes to this field take effect at
the next PWM reload event. Reads always return the values from the
temporary holding register.
Divide by 1
Divide by 2
Divide by 4
Divide by 8



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